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M61140FP
TUNER SINGLE CHIP
REJ03F0023-0120Z Rev.1.2 Apr.16.2004
Description
The M61140FP is a semiconductor integrated circuit consisting of Tuner signal processing for NTSC color TV and VCRs. The circuit includes Mixer circuit in Tuning system, Oscillator circuit, PLL frequency synthesizer and VIF/SIF, which permits a smaller tuner system.
Features
* VIF/SIF Inter carrier type for NTSC Coil-less VCO Adjustment free AFT High-speed IF AGC * PLL Low phase noise and High-speed lock-up Built-in band switch driver (4 port) I2C bus control Available for both XO and external reference * Mixer/Oscillator Built-in U&V Oscillator and mixer Built-in IF Amplifier (Unbalanced Output)
Application
TV, VCR
Recommended Operating Conditions
Supply voltage range --- 4.75 to 5.25V Recommended supply voltage --- 5.0V
Rev.1.2, Apr.16.2004, page 1 of 28
M61140FP
Pin configuration and Block diagram
Logic GND Logic Vcc IF2 GND Vt Drive VIF Vcc IF2 Vcc IF OUT
Ref IN
SDA
36
IF2 GND
35
34
33
VIF Vcc
32
31
30
Logic GND
29
28
Logic Vcc
27
26
Bus receiver
25
M/O Vcc
ADS
SCL
CP
24 23 22 21 20 19 18 17 16 15 14 13
VIF IN 2 VIF IN 1 AF Bypass
IF amp
Video det
Audio OUT QIF OUT
LIM AMP QIF AMP
Ref divider Coil-less VCO Phase det RF AGC IF AMP 15bit P.G divider PSC 1/32, 1/33
Band driver
37 38 39 40 41 42
VIF GND
MO Vcc
Charge pump
XO
RF AGC OUT PFMST PVHFL PVHFH
FM det
AFT OUT VIF GND IF AGC 1 APC Filter
Mix Filter 1 Mix Filter 2 RF GND V Band IN
AFT APC
V MIX
Video OUT VCO F/B EQ IN
IF AGC DET LPF EQ AMP
Vreg OSC GND
RF GND
Video det OUT
RF AGC Delay
OSC GND
Vreg
U OSC 1
V OSC IN 1
V OSC OUT 1
Rev.1.2, Apr.16.2004, page 2 of 28
V OSC OUT 2
V OSC IN 2
IF AGC 2
U OSC 2
EQ F/B
43 44 45 46 47 48
U MIX VHF OSC UHF OSC
PUHF U Band IN 1 U Band IN 2
1
2
3
4
5
6
7
8
9
10
11
12
M61140FP
Absolute maximum ratings (Ta=25C, unless otherwise noted)
Parameter Supply Voltage MO Block PLL Block Maximum Allowable Input Input Voltage Port Output Voltage Port Output Current (1) Port Output Current (2) Port Output Current (3) SDA Output Current Power Consumption Operating Temperature Storage Temperature Symbol Vcc Vin Vimax Vo Iopmax1 Iopmax2 Iopmax3 Iosdamax Pd Topr Tstg Ratings 6 126 6 6 26 7 33 10 750 -20 to +75 -40 to +150 Unit V dBV V V mA mA mA mA mW C C Pin25 to 27 Pin20 to 22,15 Pin20, 21 Pin15, 22 2 circuits are on at same time Recommended circuit board. When Cu occupancy area is 50%. Note
Temperature Characteristics (maximum ratings) Mounting in standard circuit board (70mmx70mmx1.6mmt Epoxy board of one side copper )
1500
Allowable power consumption Pd
1250 1000 750 500 250 0 -20
0
25 50 75 100 Ambient temperature Ta (C)
125
150
Recommended Operating Condition (Ta=25C, unless otherwise noted)
Parameter Guarantee Operating Voltage Supply Voltage Range Operating frequency of Crystal oscillator Port output current (1) Port output current (2) Symbol Vcc Vcc fopr Ioprt1 Ioprt2 Ratings 4.5~5.3 4.75~5.25 4.0 0~25 0~5 Unit V V MHz mA mA Pin 20,21 Pin 15,22 Note Refer to Data
Rev.1.2, Apr.16.2004, page 3 of 28
M61140FP
Pin Description
Pin No. 1 Pin name VIDEO DET OUT Function Video detected output terminal. SIF trap and SIF B.P.F. are connected to this terminal. Because of open emitter configuration, an externally connected drive resistor is necessary. Circuit Diagram
33
50
1
2
Vreg
Regulated voltage output. Approximately 3V output.
33
50
2
9.9K
6.2K
3
RF AGC DELAY
RF AGC terminal. This terminal combine 4.5MHz SIF signal input with set up the RF AGC delay point. The RF AGC delay point is set up by the DC component of input signal. AC component is FM detection threw the limiter amplifier.
33
40
3
5.1K 40p
43K 15p
4 44
IF AGC 2 IF AGC 1
IF AGC 2 terminal IF AGC 2 terminal. External capacitor effects AGC speed. When this terminal is grounded, the effect of VIF amp gain becomes minimum.
33
10K 2.5K 50
4 44
Rev.1.2, Apr.16.2004, page 4 of 28
M61140FP
Pin No. 5 Pin name EQ F/B Function Equalizer feedback terminal. It is possible to change the frequency characteristic of the video signal by attaching L,C,R to this terminal. Circuit Diagram
33
2.2K 500
5
7K
6 7 8 9 10
OSC GND V OSC IN 1 V OSC OUT 1 V OSC OUT 2 V OSC IN 2
OSC ground terminal. VHF oscillator circuit is connected externally. When band byte bit PUHF is set "1", bias current of oscillator transistor turns OFF.
24
600
400 600 400
9 10
7 8
2.2K
11 12
U OSC 1 U OSC 2
UHF oscillator circuit is connected externally. When band byte bit PUHF is set "1", bias current of oscillator transistor turns ON.
36
400 400 3p
11
2.5p
3p
12
2.5p
13 14
U BAND IN 1 U BAND IN 2
UHF RF input terminal. Input type is balance input. In the case of unbalance input, grounding of either pin 13 or 14 with capacitor is required, while input to the other pin.
24
13
1.8K
14
1.8K
Rev.1.2, Apr.16.2004, page 5 of 28
2.2K
M61140FP
Pin No. 15 Pin name PUHF Function Band change drive terminal. Output configuration is PNP open collector. When band selection bit PUHF is set "1", current is output. Circuit Diagram
24
47K
15
16
V BAND IN
VHF RF input terminal. Input type is unbalance.
24
2.2K
16
2.2K
17 18 19
RF GND MIX FILTER 1 MIX FILTER 2
RF (Mixer) GND terminal. Mixer output terminal. The output terminal is open collector type, single-tuned filter is connected. This pin is pull-up through power supply in order for voltage to be above 4.2V.
24
200 20p 4K
18 19
200 20p
4K
20 21
PVHFH PVHFL
Band change drive terminal. Output configuration is PNP open collector. When band selection bit PVHFL or PVHFH is set "1", current is output.
28
47K
20
21
Rev.1.2, Apr.16.2004, page 6 of 28
M61140FP
Pin No. 22 Pin name PFMST Function Band change drive terminal. Output configuration is PNP open collector. When band selection bit PFMST is set "1", current is output. Reference frequency or divided frequency of local are output by test mode condition. Circuit Diagram
28
47K
22
23
RF AGC OUT
RF AGC output terminal. It is current drive type.
33
24
50
23
24 25
MO Vcc ADS
Mixer and oscillator block power supply. Address setting input terminal. Address bit "MA1","MA2" is selected by the potential at this terminal.
28
40K 1K
25
13K
26
SCL
SCL input terminal.
28
1K
26
Rev.1.2, Apr.16.2004, page 7 of 28
M61140FP
Pin No. 27 Pin name SDA Function SDA input terminal. Reading and 2 writing of data confirm to I C bus of Philips. Circuit Diagram
28
1K
27
ACK
28 29
Logic Vcc REF IN
Logic block power supply. Reference frequency input terminal. Connect crystal oscillator at this terminal, or external signal (Sine wave).In this case of using external sine wave signal, pull down this terminal with 1.5k to 3.3k.
28
500
500
1.3K 1.3K
29
30 31
Logic GND VT DRIVE
Logic block power supply. Filter transistor drive terminal. As for drive output, control bit "OS" controls it On or OFF Charge pump output terminal. When the phase of the divide frequency of local is lead compared with the reference frequency, the "source" current state becomes active. If it is lag, the "sink" current becomes active. If the phase are the same, the high impedance state becomes active. VIF block power supply. Power supply terminal exclusively for IF amp output (pin 34) circuit. IF amp output terminal. This terminal is a low impedance and output IF frequency.
28
32
CP
32
1K 50
D
U
31
150 OS
33 34
VIF Vcc IF2 Vcc
35
IF OUT
34
20
35
36
IF2 GND
IF2 grand terminal. This grand is exclusively used by circuit of IF amplifier
Rev.1.2, Apr.16.2004, page 8 of 28
M61140FP
Pin No. 37 38 Pin name VIF IN 1 VIF IN 2 Function IF signal thew SAW filter is input. It is a balance type input. Circuit Diagram
33
37 38
2K
2K 14K
39
AF BYPASS
AF bypass terminal. It is connected to one of the input of a differential amplifier, external capacitor provides AC filtering. When resistor is connected in series with capacitor, it is possible to lows the amplitude of the audio output. When audio output terminal is not used, please connect pin 22 to GND. Sound output terminal. Deemphasis is achieved by external components.
33
37 38
2K
2K 14K
40
AUDIO OUT
33
200
40
41
QIF OUT
QIF output terminal. FM signal which is converted to 4.5MHz is output. Additionally, this pin has dual function of being VIF VCO type selection. Connected to GND via 1.2k
33
400 30K
6p
41
Rev.1.2, Apr.16.2004, page 9 of 28
M61140FP
Pin No. 42 Pin name AFT OUT Function AFT output terminal. Because of pulse-like signal output, a smoothing capacitor is connected externally. In addition, AFT detection sensitivity is set by external resistor. Circuit Diagram
33
300u
50
42
300u
43 45
VIF GND APC FILTER
VIF GND terminal. APC filter terminal. It is the loop filter terminal which a VIF signal is made to lock VCO and keeps frequency constant.
28 33
21K 30 0
17 45
21K
30 0
46
VIDEO OUT
Video output terminal. The signal inputted into the EQI terminal is outputted.
33
200
46
47
VCO F/B
VCO feedback terminal. The feedback is to keep the freerunning frequency of the built-in VCO.
33
20K
10K
47
Rev.1.2, Apr.16.2004, page 10 of 28
M61140FP
Pin No. 48 Pin name EQ IN Function The video signal threw the SIF trap is input to this terminal. DC impression from pin 1 is required for the input to 48 pins. Circuit Diagram
33
100
48
Setting Data
M61140FP's bus format is based on Philips's I2C-bus. Bidirectional bus communication control can be performed. It consists of WRITE mode which receives various data, and READ mode which transmits data. Recognition in WRITE mode and READ mode is performed by specification of the last bit on Address Byte (R/W bit). When the setup of a R/W bit is "0", it is set as WRITE mode and, in the case of "1", is set as READ mode. Furthermore, it has the address in which four programs are possible. It enables this to use two or more devices on the same I2C bus. Moreover, four programmable addresses are possible. Therefore, two or more devices become usable on I2C bus. A setup of an address is chosen by the voltage impressed to an address setting terminal (ADS:25 pin). If the address Byte in agreement is received, a data line will be set to "L" between knowledge, and at the time of WRITE mode, if Data Byte is received, SDA line between knowledge will be set to "L." It shows a definition of bus protocol admitted in the following. Mode_1 STA Mode_2 STA Mode_3 STA Mode_4 STA CA DB1 DB2 CB1 CB2 STO CA CB1 CB2 DB1 DB2 STO CA DB1 DB2 STO CA CB1 CB2 STO STA : Start condition STO : Stop condition CA : Chip address DB1 : Divider data byte 1 DB2 : Divider data byte 2 CB1 : Control data byte 1 CB2 : Band data byte 2
Rev.1.2, Apr.16.2004, page 11 of 28
M61140FP (1) WRITE mode The information of 5 bytes required for circuit operational chip address, control data and band SW data of 2 bytes and divider data of 2 bytes. after the chip address input, 2 or 4 bytes can be received. Function bit is contained in the first and the third data byte to distinguish between divider and 'control data/band SW data', with "0" going ahead of divider data, and "1" going ahead of 'control data/band SWdata'. The timing of Writing data for bus protocol Mode is shown in the figure below. Divider data uses 15 bits and is read in at the rise of the eighth clock bit of the second byte divider data (DB2). Control data (CB1) and band SW-data (BB) are each read in at the rise of their eighth clock bit. Timing Chart
SDA address CB2
DB1
DB2
CB1
SCL
Read into latch Read into latch Read into latch
Write mode data format
Byte Address Byte (CA) Divider Byte1 (DB1) Divider Byte2 (DB2) Control Byte (CB1) Band Byte (CB2) MSB 1 0 N7 1 X 1 N14 N6 CP X 0 N13 N5 T2 X 0 N12 N4 T1 X 0 N11 N3 T0 PUHF MA1 N10 N2 Rsa PFMST MA0 N9 N1 Rsb PVHFH LSB R/W=0 N8 N0 OS PVHFL A A A A A
Programmable Address Bit
Address input voltage applied to ADS [V] 0 to 0.1xVcc Open or 0.2 to 0.3xVcc 0.4xVcc to 0.6xVcc 0.9xVcc to Vcc MA1 0 0 1 1 MA0 0 1 0 1
N14 to N0 : Set up for division ratio of the programmable divider Frequency of VCO fvco: fvco=fref x N Division ratio N: N=N14(2^14 )+N13(2^13 )+ --- +N0(2^0) Range of division ratio N: N=1,024 to 32,767 fref: Reference frequency of phase comparator CP: Set up the charge pump current
CP 0 1 Charge pump current * 70A 300A
Note:* Current of charge pump is typ current
In the case of setting current 270A,when PLL is locked, charge pump current is automatically switched to CP=O (70A).
Rev.1.2, Apr.16.2004, page 12 of 28
M61140FP T2, T1, T0 : Set up for test mode
CP 0 1 X X X 0 1 0 T2 0 0 0 1 1 1 1 1 T1 0 0 1 1 1 0 0 0 T0 X X X 0 1 0 X 1 Charge pump CP switched off CP switched on High impedance Sink Source High impedance CP switched on High impedance Test output fREF f1/N Test SW OFF OFF OFF OFF OFF OFF ON OFF Mode Normal mode Normal mode Test mode Test mode Test mode Test mode TV test mode Test mode
Note : fREF and f1/N is available on pin PFMST(pin 22). Test SW is for the mix filter damping switch
Rsa : Set up tuning step
Rsa 0 1 X Rsb 1 1 0 Division ratio 1/128 1/64 1/80 tuning step frequency @4MHz X'tal 31.25kHz 62.5kHz 50.0kHz
OS : Set up drive output
OS 0 1 Drive output ON OFF("L")level Mode Normal mode Test mode
PFMST, PUHF , PVHFL,PVHFH : PORT setting
PFMST,PUHF,PVHFL,PVHFH 0 1 Output OFF ON
PNP open collector output. When PUHF is "OFF", Mixer and Oscillator active VHF mode.
(2) READ mode data format At the time of READ mode, a power-on reset state, a phase comparison machine lock detector output state, and the state of the charge pump current change SW are outputted to a master device. Read mode data format
Byte Address Byte Status Byte MSB 1 POR 1 FL 0 ACPS 0 X 0 X MA1 X MA0 X LSB R/W=1 X A A
X: 0 or 1 Don't care POR: Power on reset flag. Output is "1" at power-on Set to "1" when the time of a power supply voltage injection or power supply voltage falls in about 3V or less. Reset by "0", if a Request to Send is carried out in READ mode and a flag is returned. Power supply voltage is about 3v or more, Reset by "0", after returning a flag in READ mode. FL: Lock detector flag. Output is "1" at locked, output is "0" at unlocked. ACPS: Automatic charge pump current flag. Output is "0" at charge pump current automatically switched mode, output is "1" at other mode.
Rev.1.2, Apr.16.2004, page 13 of 28
M61140FP (3) Power on reset The initial status is shown as below when supply voltage is turned on. If supply voltage becomes less than about 3.0V, the initial status is set.
Byte Divider Byte1 (DB1) Divider Byte2 (DB2) Control Byte (CB1) Band Byte (CB2) MSB 0 X 1 X X X 1 X X X 0 X X X 1 X X X X 0 X X 1 0 X X 1 0 LSB X X 1 0
(4) Data format example Ex1.US-TV-ch2 (fRF=55.25MHz,fosc=101MHz),CP sw=ON, Reference Frequency=4MHz,31.25kHzstep, PUHF="ON"
Byte Address Byte Divider Byte1 (DB1) Divider Byte2 (DB2) Control Byte (CB1) Band Byte (CB2)
6
MSB 1 0 1 1 X
3
LSB 1 0 0 1 X 0 0 1 0 X 0 0 0 0 X 0 1 0 0 0 MA1 1 0 0 0 MA0 0 0 1 0 R/W=0 0 0 0 1 A A A A A
Divide ratio N =101*10 /31.25*10 = 3232 11 10 7 5 = 2 +2 +2 +2
Purchase of Renesas Technology electric corporation's I C components conveys a license under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips
2
2
Rev.1.2, Apr.16.2004, page 14 of 28
M61140FP
Electrical Characteristics
DC characteristics (Ta=25C, Vcc=5.0V otherwise noted.)
Measure point 33 34 24 28 28 28 Input SG Condition switches set to position "1" unless otherwise noted SW33=2 SW34=2 SW24=2 SW28=2 Port OFF SW28=2, Io(PVHFL) or Io(PVHFH)=20mA SW28=2, Io(PFMST) or Io(PUHF)=5mA Limits min 40 14 14 11 27 15 typ 53 19 18 14 37 20 max 66 24 23 18 46 25 Unit mA mA mA mA mA mA Note
Item IF Vcc current IF2 Vcc current M/O Vcc current Logic Vcc current(1) Logic Vcc current(2) Logic Vcc current(3)
Symbol IccIF IccIF2 IccRF IccLo1 IccLo2 IccLo3
Rev.1.2, Apr.16.2004, page 15 of 28
M61140FP Mixer and OSC Block (Ta=25C, Vcc=5.0V otherwise noted.)
Measure point 35,16 35,16 35 35 35 Input SG Condition switches set to position "1" unless otherwise noted fRF=55.25MHz, CW fRF=361.25MHz, CW fRF=55.25MHz, CW fRF=361.25MHz, CW fd=55.25MHz, CW fud=fd6MHz, AM100kHz, 30% fd=361.25MHz, CW fud=fd6MHz, AM100kHz, 30% fp=241.25MHz, fs=245.75MHz fc=244.83MHz, AM100kHz, 30% fp=241.25MHz, fs=245.75MHz fc=244.83MHz, AM100kHz,30% fRF=367.25MHz, CW fRF=801.25MHz, CW fRF=367.25MHz, CW fRF=801.25MHz, CW fd=367.25MHz, CW fud=fd-6MHz, AM100kHz, 30% fd=367.25MHz, CW fud=fd+6MHz, AM100kHz, 30% fd=801.25MHz, CW fud=fd-6MHz, AM100kHz, 30% fd=801.25MHz, CW fud=fd+6MHz, AM100kHz, 30% fp=615.25MHz, fs=627.75MHz fc=618.83MHz, VoIF=-10dBm Limits min 20 20 -28 typ 23 23 16.5 17.5 -25 max 26 26 18 20 Unit dB dB dB dB dBm Note
Item V H F Conversion gain1 Conversion gain2 NF1 NF2 Cross modulation1
Symbol GvcV1 GvcV2 NFV1 NFV2 CMV1
Cross modulation2
CMV2
35
-
-28
-25
-
dBm
CS beat1
CS1
35
-
55
60
-
dBc
CS beat1
CS2
35
-
55
60
-
dBc
U H F
Conversion gain3 Conversion gain4 NF1 NF2 cross modulation1(-) cross modulation1(+) cross modulation2(-) cross modulation2(+) CS beat3
GvcU3 GvcU4 NFU1 NFU2 CMU1(-)
35 35 35 35 35
-
27 27 -31
30 30 11.5 13 -28
33 33 13 15 -
dB dB dB dB dBm
CMU1(+)
35
-
-37
-34
-
dBm
CMU2(-)
35
-
-31
-28
-
dBm
CMU2(+)
35
-
-37
-34
-
dBm
CS3
35
-
55
60
-
dBc
Rev.1.2, Apr.16.2004, page 16 of 28
M61140FP Mixer and OSC Block (Ta=25C,Vcc=5.0V otherwise noted.)
Measure point 35 Input SG Condition switches set to position "1" unless otherwise noted fp=83.25MHz, fs=87.75MHz VoIF=-10dBm fp=91.25MHz, VoIF=-10dBm fp1=83.25MHz, fp=77.25MHz VoIF=-10dBm fosc=183MHz fosc=366MHz fosc=732MHz Vcc=10% VccOn 3sec to 5min fp=83.25MHz, VoIF=-10dBm +/-50kHz offset fp=241.25MHz, VoIF=-10dBm +/-50kHz offset Vcc =10% VccOn 3sec to 5min fp=615.25MHz, VoIF=-10dBm +/-50kHz offset Limits min 55 typ 60 max Unit dBc Note
Item B e a t 6ch beat
Symbol INT6ch
A5ch beat 5ch beat
INTA5ch INT5ch
35 35
-
60 60
65 65
-
dBc dBc
PSC beat1 PSC beat2 PSC beat3 O S C VHF OSC Power supply shift VHF OSC Swon Drift VHF OSC C/N1
PSC183 PSC366 PSC732 fosc_v foscv_t C/N(V1)
35 35 35 35 35 35
-
65
-
-85 -85 -85 500 500 -
dBm dBm dBm kHz kHz dBc
VHF OSC C/N2
C/N(V2)
35
-
65
-
-
dBc
UHF OSC Power supply shift UHF OSC Swon Drift UHF OSC C/N
fosc_u foscu_t C/N(U)
35 35 35
-
55 65
-
500 -
kHz kHz dBc
Rev.1.2, Apr.16.2004, page 17 of 28
M61140FP PLL Block (Ta=25C,Vcc=5.0V otherwise noted.)
Condition switches set to position "1" unless otherwise noted SW26,27=2 SW26,27=2 SW25A,26,27=2 Vi=4.0V SW25A,26,27=2 Vi=0.4V SW25A,27=2 Io=3mA SW25A,27=2 Vo=5.0V SW25,25A=2 Vi=5.0V SW25,25A=2 Vi=0.4V SW20,21=2 Io=-25mA SW15,22=2 Io=-5mA SW15,20,21,22=2 output "OFF" SW32=2 Vo=2.5V SW32=2 Vo=2.5V SW32=2 Vo=2.5V,output "OFF" SW31=2 Vo=0.5V
Item S D A / S C L S D A A D S P O R T C P High input voltage Low input voltage High input current Low input current
Symbol ViH ViL IiH IiL
Measure point 26,27 26,27 26,27 26,27
Input SG -
Limits min 2.3 typ -1 max Vcc 1.0 10 -10 Unit V V A A Note
Low output voltage Leakage current High input current Low input current Output voltage1 Output voltage2 Leakage current High output current Low output current Leakage current
VoSL IoSLK ViAH IiAL Vop1 Vop2 IopLK IcpH IcpL IcpLK Iovt fxin
27 27 25 25 20,21 15,22 15 20~22 32 32 32 31 29
-
4.6 4.6 170 55 3.2
4.8 4.8 300 75 4.0
0.4 10 600 -200 10 400 115 50 2.0 4.4
V A A A V V A A A nA mA MHz
V T X i n
Tuning drive output Operational frequency of Crystal OSC Absolute Value Sensitivity of External signal
Rxin Vixin
29 29,22
SG17
SW29=2,Sine wave signal input Data(T2,T1,T0)="01X"
2.0 50
-
600
k mVp -p
*14
Rev.1.2, Apr.16.2004, page 18 of 28
M61140FP Data input Block (Ta=25C,Vcc=5.0V otherwise noted.)
Measure point 26 27 27 26 26 26,27 26,27 26,27 26,27 26,27 26 Input SG Condition switches set to position "1" unless otherwise noted Limits min 0 1.3 0.6 1.3 0.6 0.6 0 100 0.6 typ 100 max 400 300 300 Unit kHz sec sec sec sec sec sec nsec nsec nsec sec Note
Item Clock frequency Bus free time Data hold time SCL LOW hold time SCL HIGH hold time Set up time Data hold time Data set up time Rise time Fall time Set up time
Symbol fSCL tBUF tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tR tF tSUSTO
Timing chart
SDA
tBU tLOW tr tf tHDSTA
SCL
tHDSTA [STOP] [START] condition condition tHDDAT tHIGH tSUDAT tSUSTA [START] condition tSUSTO [STOP] condition
Rev.1.2, Apr.16.2004, page 19 of 28
M61140FP VIF Block1 (Ta=25C, Vcc=5.0V otherwise noted.)
Measure point 46 46 46 1 1,37,38 1,37,38 46,37,38 46,37,38 1 1 1 37,38 37,38 23 23 23,37,38 Input SG SG1 SG2 SG2 SG3 SG4 SG5 SG9 SG9 SG11 SG12 SG12 SG6 SG7 SG8 @3pin open DC 40MHz Vo=-3dB point Vo=-3dB point GR = VinMAX - Vin MIN 5MHz LPF Condition switches set to position "1" unless otherwise noted Limits min 0.85 1.1 48 6 101 52 0.6 1.1 32 4 0 82 typ 1.15 1.3 50 7 45 105 60 0.8 1.5 40 3 3 2k 5 4.3 0.3 85 max 1.35 1.5 52 5 5 4.6 0.6 88 Unit Vp-p V dB MHz dBV dBV dB MHz MHz dB % deg pF V V dBV *9 *1 *2 *3 *4 *5 *6 *7 *8 Note
Item Video output level Sync tip voltage Video S/N Video out freq. response Input sensitivity Max. IF input AGC range Capture range U Capture range L Inter modulation D/G D/P Input impedance Input capacitance RF AGC max voltage RF AGC min voltage RFAGC Delay point
Symbol Vodet VoSNK VideoS/ N BW VinMIN VinMAX GR CR-U CR-L IM DG DP Zin Yin V23H V23L Vi23
VIF Block2 (Ta=25C,Vcc=5.0V otherwise noted.)
Measure point 42 Input SG SG17 Condition switches set to position "1" unless otherwise noted SW42,29=2,44pin "GND" Data (T2,T1,T0="01X") @360k/360k 0.1F 4.3 0 frequency=58.75MHz frequency=45.75MHz Limits min -500 typ max 500 Unit kHz Note *15
Item Freerun frequency
Symbol fvco
AFT Sensitivity AFT high output voltage AFT Low output voltage AFT center voltage AFT center voltage
V42H V42L V42C1 V42C2
42 42 42 42 42
SG10 SG10 SG10 SG18 SG2
12 4.7 0.3 2.4 2.4
24 5 0.7 2.5 2.5
36 V V 2.6 2.6
mV/ kHz
*10
V V
Rev.1.2, Apr.16.2004, page 20 of 28
M61140FP SIF Block (Ta=25C,Vcc=5.0V otherwise noted.)
Measure point 40 40 40 3,40 40 41 Input SG SG13 SG13 SG16 SG14 SG15 SG16 Condition switches set to position "1" unless otherwise noted SW3=2 @Pin39:0.22F SW3=2 @Pin39:0.22F SW3=2 @Pin39:0.22F SW3=2 S/N=30dB Point SW3=2 SW3=2 Limits min 500 51 44 86 typ 770 0.4 56 50 50 92 max 1040 0.9 55 Unit mVrms % dB dBV dB dBV *11 *12 *13 Note
Item Audio out level Audio out THD AF S/N Limiting sensitivity AMR QIF output
Symbol VoAF THDAF AF S/N LIM AMR VoQIF
Measurement diagram
Vt
33V 22K 100p 10p 18K 2200p 0. 1 1u 5V 5V 1 21 2 4MHz
0. 01 01u
I2C BUS
5V 1 S W25A 1 2 1 SW 27 2 SW 25 SW 26 2 2
A
2 1 SW 29 1
A A
1n 1 1 2 SW 34 10 n 2 SW 33 47 47u 0. 01u 01 SW 32 SW 31
1
2
A
SW 28
TP 35
V
A
5V
0. 01u 01
10p
A
1 2
36
IF 2 GN D
35
34
33
32
31
30
Log ic G N D
29
28
Log ic Vcc
27
26
25
M/O Vcc
IF 2 V cc VI F Vc c
IF a mp
Video det
VIF in
23
Char ge pump
XO
Bu s rec eiv er
24
SW 24 0. 01u 01
37 38
TP 23
0. 1u 1 1 10K
1n 50 0. 22 0
B and driver
FM det LI M AMP QI F AMP AF T APC RF AG C 15bit P G d ivider .
VI F G N D
22
V
2
TP 40 TP 41
1n 5V 0. 01u 01 7.5K
21
360K
19
TP 42
2 360K 1 SW 42 1 SW 44 1000p 0. 22
Ph as e det IF AMP
RF G N D
20
0. 1u 1
0. 1u 1
17
18
39 40 41 42 43 44
0. 01u SW 22 01 1 SW 21 2
Re f divider Coil-les s VC O
0. 01u 01
SW 22
1
0. 01u 2 01 27p 50 2.2K
27p
2
V4 6A V4 6B LP F
200 1
2
SW 46
47p 0. 1u 1
U MIX UH F OS C
15
IF A G C DE T LP F EQ AMP
Vr eg OS C GN D
PS C 1/32, 1/33
16
V MIX
V ba nd in
1n
14
15 u 330
1
240
2
0. 01u 01
3
10K
4
5
TP 4
6
5p 68
7
5p
8
5p
9
5p
10
1n
11
10p
12
2200p
22K SW 3
0. 022u 022 2p
56p
13
TP 1
Rev.1.2, Apr.16.2004, page 21 of 28
45 46 47 48
1 56p 7. 5K 22 u 50 2 1n 10 K
SW 15 1n 1n
1
2
VH F OS C
1n
U band in
5. 6K 0. 5p
1K
2. 7K
100K
2200p 100K 2200p 6800p 27K 100K 27K
2200p
Vt
M61140FP INPUT SIGNAL
SG 1 2 3 4 5 6 7 8 9 10 11 50ohm termination f0=45.75MHz f0=45.75MHz f1=45.75MHz f2=Frequency Variable f0=45.75MHz f0=45.75MHz f0=45.75MHz f0=45.75MHz f0=45.75MHz f0=Frequency Variable f0=Frequency Variable f1=45.75MHz f2=42.17MHz f3=41.25MHz f0=45.75MHz f0=4.5MHz f0=4.5MHz f0=4.5MHz f0=4.5MHz f0=4.0MHz f0=58.75MHz Vi=90dBV Vi=90dBV Vi=90dBV Vi=70dBV Level Variable Level Variable Vi=80dBV Vi=110dBV Level Variable Vi=90dBV Vi=90dBV Vi=90dBV Vi=80dBV Vi=80dBV Sync Tip Level 90dB 10 stair-steps waveform Vi=90dBV Level Variable Vi=90dBV Vi=90dBV Level Variable Vi=90dBV fm=20kHz CW CW CW fm=20kHz fm=20kHz CW CW CW fm=20kHz CW CW CW CW TV moduration=87.5% fm=1kHz fm=1kHz fm=1kHz CW CW CW +/- 25kHz dev +/- 25kHz dev AM=30% AM=77.8% AM=77.8%
mixed signal AM=77.8% AM=14.0%
mixed signal
12 13 14 15 16 17 18
Rev.1.2, Apr.16.2004, page 22 of 28
M61140FP
Measurement of electrical characteristic Notes
1. Video S/N Input SG2 to VIF IN and measure the video out (Pin 46) noise in r.m.s. at TP46B through a 5MHz (-3dB) L.P.F.
S/N=20log 0.7xVodet NOISE (dB)
2. Video Band Width 1. Measure the 1MHz component level of Video output TP1 with a spectrum analyzer when SG3 (f2=44.75MHz) is input to VIF IN. At that time, measure the voltage at TP44 with SW8, set to position 2, and then fix V8 at that voltage. 2. Reduce f2and measure the value of (f2-f1) when the (f2-f1) component level reaches -3dB from the 1MHz component level as shown below.
Video det out -3dB
1MHz
BW
(f2-f1)
3. Input sensitivity Input SG4 (Vi=90dB) to VIF IN , and then gradually reduce Vi and measure the input level when the 20kHz component of Video output TP46A reaches -3dB from Vo det level. 4. Maximum Allowable Input 1. Input SG5 (Vi=90dB) to VIF IN, and measure the level of the 20kHz component of Video output. 2. Gradually increase the Vi of SG and measure the input level when the output reaches -3dB. 5. AGC control Range GR=VinMAX-VinMIN (dB) 6. Capture range U 1. Increase the frequency of SG9 until the VCO is out of locked-oscillation 2. And decrease the frequency of SG9 and measure the frequency fU when the VCO is locked. CR-U=fU-45.75 (MHz) 7. Capture range L 1. Decrease the frequency of SG9 until the VCO is out of locked-oscillation. 2. And increase the frequency of SG9 and measure the frequency fL when the VCO is locked. CR-L=45.75-fL (MHz) 8. Inter modulation 1. Input SG11 to VIF IN, and measure video output TP9 with an oscilloscope. 2. Adjust AGC filter voltage V44 so that the minimum DC level of the output waveform is 1.5V. 3. At that time, measure TP1 with a spectrum analyzer The inter modulation is defined as a difference between 0.92MHz and3.58 MHz frequency components. 9. RF AGC Operating Voltage: Input SG8 to VIF IN and gradually reduce Vi and then measure the input level when RF AGC output reaches 1/2Vcc, as shown below.
V23 V23H 1/2Vcc V23L
Vi
Rev.1.2, Apr.16.2004, page 23 of 28
M61140FP 10. AFT sensitivity, Maximum AFT voltage, Minimum AFT voltage 1. Input SG10 to VIF IN, and set the frequency of SG10 so that the voltage of AFT output TP42 is 3(V). This frequency is named f(3). 2. Set the frequency of SG10 so that the AFT output voltage is 2(V). This frequency is named f(2). 3. IN the graph shown below, maximum and minimum DC voltage are V42H and V42L, respectively.
V42 1000mV f(2)-f(3) (KHz) 3V (mV/KHz) 2V f(3) f(2) V42L V42H
=
11. AF S/N 1. Input SG19 to LIM IN, and measure the output noise level of Audio output (TP40). This level is named VN.
S/N=20log VoAF VN
(dB)
12. Limiting Sensitivity 1. Input SG14 to LIM IN, and measure the 1kHz component level of AF output TP40. 2. Input SG17 to LIM IN, and measure the noise level of AF output TP40 . 3. The input limiting sensitivity is defined as the input level when the difference between each 1kHz components of audio output (TP40) is 30dB, as shown below.
AF Audio output while SG14 is input. 30dB Audio output while SG17 is input.
13. AM Rejection 1. Input SG15 to LIM IN, and measure the output level of Audio output (TP40). This level is named VAM. 2. AMR is
AMR=20Log
Vo AF (mVrms) VAM (mVrms)
(dB)
14. Xin sensitivity of external signal 1. Input data that Control byte data CP,T2,T1,T0 is "0100" and Rsa,Rsa is"01" 2. The Reference frequency is output to Pin 22, measure the frequency with counter. 3. Input sensitivity is defined as the input level when the frequency is less than plus-or-minus 1ppm of 31.25kHz. 15. Freerun frequency 1. Input data that Control byte data CP,T2,T1,T0 is "01X". 2. The Reference frequency is output to Pin 42, measure the frequency with counter. This frequency is named fmoni. Freerun frequency (foUS) is 52.9524[MHz] - fmoni x 9 [MHz] Freerun frequency (foJP) is 65.9512[MHz] - fmoni x 9 [MHz]
Rev.1.2, Apr.16.2004, page 24 of 28
M61140FP
Application board example
Rev.1.2, Apr.16.2004, page 25 of 28
*20
Vt
100p 10 p 5V
33 V 22K 0. 01
Re f in ( 4MHz )
*1 *5
M61140FP
to MO D SD A S CL A DS
5V 1n
18K 5V 2200p 0. 1 47 0. 01 0. 01
*14
0. 01
*13
36
*2 *15
IF 2 G ND VI F V cc Log ic G ND Log ic V cc
5V
Application Example
35
24
34
33
32
31
30
29
28
27
26
25
M/ O V cc
37
XO Bu s rec eiv er
*19
0. 01
IF a mp
23
V ideo det
38
1n 1n
SA W
Ch arge pump
RF A GC otu
0. 1
Rev.1.2, Apr.16.2004, page 26 of 28
22 39
FM det
0.22 0. 01
*18 *17
0. 01
PF MS T PV HFL PV HF H
21
40
A udio out QI F out
7.5K
0. 01
LI M AMP
Re f divider
20
B and dr iver
41
0. 01
5V
1. 5K for J AP A N mode
Co il-les s VC O Ph as e det RF AG C IF AMP
360K
19
42
AF T out AF T APC 15bit P.G d ivider V MIX IF A G C DE T LP F EQ AMP
Vr eg
15 330 0.022 0. 1 240 68 5p 5p 5p 5p 1n 10p
QI F AMP
27p 50
2.2K
0. 1
360K
*9
18
43
0. 1
VI F G N D
17
44
27p
RF GND
1000p
16
45
V ba nd in
1n
200 27K 47p
0.22
15
46
V ideo out
0. 1
PS C 1/32, 1/33 U MIX
*16
1n
PU H F
0. 01
14
47 48
OS C GN D
VH F OS C
UH F OS C
1n
U ban d in
13
1
2
3
4
5
6
7
8
9
10
11
12
*7 *6
2p 10K 2200p 0.5p 100K 56p 0. 01 5. 6K 1K 2200p
*3
RF A GC delay
56p 22
*21
*12 *4
7.5K 2200p
*11
100K
27K *7
100K
*10
2. 7K 27K
2200p
Vt
6800p
*8
M61140FP
Application Note
*1 *2 *3 *4 *5 *6,7 *8 *9 *10 *11 *12 *13,14 *15 *16-19 *21 2SC2735 equivalent made by Renesas 45.75MHz SAW Filter made by EPCOS 4.5MHz Trap made by Murata 4.5MHz B.P.F. made by Murata HC-49/U equivalent made by Daishinku. Load capacitance=20pF,Motinal resistance: Less 300 HVC306B equivalent made by renesas MA2S77 equivalent made by MATSUSHITA 0.1mm 3mm 6t x2 P886ANS-0194VN made by TOKO 0.5mm 2.4mm 2.5t 0.5mm 2.4mm 2.5t 0.5mm 2.4mm 8.5t The bypass capacitor of Vcc is arranged near the LogicGND pin. In order to mitigate the surroundings lump by the VIF input, the balanced connection from a SAW filter to the VIF input pin of 37.38 recommends a putter which serves as a 1t coil by Tip C or the jumper. In order to stop digital beat which goes via the port output from Logic Vcc, bypass capacitor arranged near the port output pin. It is high impedance. keep away from VideodetOUT and EQ F/B pin.
Notes about the handling of IC *20 The direct power supply impression to Vt terminal is forbidden. When power supply impression is required, please impress through the resistance for current restrictions. Depending on the case, it is drive current from 31 pin, and excessive collector current flows and breaks to an external transistor. Because there is a possibility of also destroying IC by the destruction. Since this IC is using the detailed process, be careful of serge enough. Especially careful 1,7,8,9,10,25,26,27,32,48 pins.
*
Rev.1.2, Apr.16.2004, page 27 of 28
M61140FP
48P6Q-A
Plastic 48pin 77mm bodLQFP y
Weight(g) -- Lead Mater ial C u Allo y J E DE C C ode --
MMP
MD
e
Package Dimensions
E IAJ P ackage C ode LQF P 48-P -77-0.50
HD D
37
E
12
25
13
24
HE
A2
A3
A1
y
M
c
Rev.1.2, Apr.16.2004, page 28 of 28
36
48
1
S ymbol
A F L1
e
A A1 A2 b c D E e HD HE L L1 Lp
A3
L Detail F
Lp
b
x
b2 I2 MD ME
b2
I2 R ecommended Mount P d a
x y
Dimens ion in Millimeters Min Nom Max -- -- 1.7 0.1 0.2 0 1.4 -- -- 0.17 0.22 0.27 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.5 -- -- 8.8 9.0 9.2 8.8 9.0 9.2 0.35 0.5 0.65 1.0 -- -- 0.6 0.75 0.45 -- 0.25 -- -- 0.08 -- 0.1 -- -- 0 8 -- 0.225 -- -- 1.0 -- -- 7.4 -- -- -- -- 7.4
ME
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
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